Unprotect should be performed, and two additional don’t care bits (see Table 10-2 ). Any addi-
tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the
SPRL bit in the Status Register will be modified and the WEL bit in the Status Register will be
reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before
the Write Status Register command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global
Protect/Unprotect” section on page 14 for more details.
The complete one byte of data must be clocked into the device before the CS pin is deasserted;
otherwise, the device will abort the operation, the state of the SPRL bit will not change, no
potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register
will be reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
command will be ignored, and the WEL bit in the Status Register will be reset back to the logical
“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Table 10-2.
Write Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPRL
X
Global Protect/Unprotect
X
X
Figure 10-2. Write Status Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
OPCODE
STATUS REGISTER IN
SI
0
0
0
0
0
0
0
1
D
X
D
D
D
D
X
X
MSB
MSB
SO
HIGH-IMPEDANCE
22
AT26DF161
3599H–DFLASH–8/09
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